Hello! I have system where I want to transfer data to HPS memory using custom IP in FPGA during the boot process (before U-Boot stage). Does the
Hi, I want to use the FPGA to HPS SDRAM Interface, in kind of an Avalon MM Bidirectional 64 Bit. Logic is done, simulation results are as
Perhaps a simple example of taking a push button output (an HPS button?), storing it in DDR3 memory, and turning on an FPGA led...? That way I can begin to understand both the device driver, the Qsys, the Quartus, and the pin-layout aspects of dealing with DDR3 and f2h...
Hello, I'm doing a project with Arria V SoC using the HPS and FPGA parts. In the FPGA, I have a custom IP with AXI Master interface on it.
we want to use the FPGA to HPS SDRAM bridge in our u-boot linux environment. We use the altera u-boot-socfpga uboot. Every first time the kernel hang/crashes, if we want to write trough the bridge. After an warm reset everything works, we change ...
Afterwards I used the address span extender to reduce the 4GB hps in a smaller window of 256MB. I choose 32bit for Datapath width and configured the windows to the sizes. I export the windowed slave to an upper level. The name of the exported extender is appl_subsystem_...
I want to use the fpga to sdram path in Arria 10 HPS. I want to connect a 256bit AXI interface operating at 125 Mhz from a third party IP to this port. I had a couple of questions: I cannot select a 256 bit data width in HPS ...
Hi I was wondering if the address issued by the FPGA IP on the FPGA-TO-HPS SDRAM is the physical address of the SDRAM or he virtual address ? Can
2.2.2.1. FPGA to HPS Subordinate 2.2.2.2. FPGA to SDRAM Subordinate 2.2.2.3. HPS to FPGA Manager 2.2.2.4. Lightweight HPS to FPGA Manager 2.2.3. DMA Controller Interface 2.2.4. Interrupts 2.3. SDRAM 2.4. HPS Clocks, Reset, Power ...
Enable System MMU Ports option enables the SMMU (TBU) ports on the FPGA-to-HPS path. This feature supports virtual addressing of the DDR/HPS and exposes the two f2sdram ports, ARUSER and AWUSER port at top-level. When this bridge is enabled, the interfaces: f2sdram, f2sdram_axi_clock...