Prepare Analog Devices Linux kernel source code (only need to run once): sudo apt install flex bison libssl-dev device-tree-compiler u-boot-tools -y cd openwifi/user_space; ./prepare_kernel.sh $XILINX_DIR ARCH_BIT (For Zynq 7000, ARCH_BIT should be 32, for Zynq MPSoC, ARCH_BIT shoul...
All code is formatted usingclang-formataccording to the style rules in.clang-format(LLVM based with increased indent widths and brace wraps after classes). To automatically format all source code, runmake clangformat. See the wiki for additional documentation on the architecture API. ...
Editing the bootloader source code Editing the bootloader device tree when a device tree is usedAgilex™ 7, and Agilex™ 5, Stratix® 10 SoC Handoff For Agilex 7, and Agilex 5, Stratix 10 SoC the handoff information is part of the FPGA configuration bitstream.Arria...
User library project: is a collection of source code compiled to create a single library archive file (.a). Libraries often contain reusable, general-purpose functions that multiple application projects can share. A collection of common arithmetical functions is one example. BSP ...
VectorBlox SDK empowers AI/ML developers with tools for efficient Convolutional Neural Network (CNN) inference on PolarFire FPGAs and PolarFire SoC FPGAs. Access development tools, detailed documentation and practical examples on GitHub for your vision projects. Browse VectorBlox SDK on GitHub Smart...
2x16 character display driver: https://opencores.org/projects/wb_lcd The next sections will describe the features of the various sub-systems, their development and the design decisions made. Digital architecture: All of the FPGA cores run at a 36MHz base clock and the numeric oscillator, DDS...
The projects in this repo with the "_dual" postfix are intended to be used with two loaded SSDs as shown in the above image. The dual designs may not function as expected if only one SSD is loaded. If you are using the older version FPGA Drive FMC (Rev-B) with only one M.2 con...
The evaluation project contains all the source files needed to build a system that can be used to configure the ADAS3023 and capture data from it. The system consists of a Nios II softcore processor that is implemented in the FPGA found on the CED1Z board and a PC application. The softcor...
Projects Security Insights Additional navigation options main BranchesTags Code Folders and files Name Last commit message Last commit date Latest commit History 225 Commits .github/workflows .vscode benchmarks doc src .gitignore Doxyfile LICENSE ...
This is the development trunk for the Verilog-to-Routing project. Unlike the nicely packaged releases that we create, you are working with code in a constant state of flux. You should expect that the tools are not always stable and that more work is needed to get the flow to run. ...