be sent to slave after initializationreg [7:0] rd_data_cmd_pad[1:0];reg [7:0] cmd2tx_din;reg [7:0] rd_data_cmd;reg [3:0] div10_cnt; //the time while div10_cnt=0 and div10_cnt=0- equals to an SCK period reg [2:0] sck_cnt8; //sck_cnt8=7 indicates that 8bits h...
ISE是Xilinx早期FPGA开发工具，实现逻辑综合和布线等功能，例如Spartan3到Spartan6等，到Spartan6之后，其实...
reg rd_spidata_cmd_cnt_en; reg send_rd_spidata_cmd_n; reg rd_data_cmd_rd_en; reg [15:0] bytecnt; reg [5:0] incr; reg tx_wr_en; reg tx_rd_en; reg rx_wr_en; reg transmision_done; reg addr; reg delaycnt_ctrl_n; reg transfer_n; //data transfer enable bit,active low...