Solved: IMX6 processor with fly by topology routing meets the timing wrt to the JEDEC specification but the voltage levels are less than 1V where it
The fly-by topology for DDR3 is not supported on the i.MX7D as the memory controller is not capable of automatically calibrating each DQS strobe to arrive at the DRAM in phase with the SDCLK signal. This calibration is critical for the DDR3 to work at any speed. The most likel...
We have routed DDR3 address and command lines as per fly by topology in our design . Do we need to make any changes in u-boot and OS files due to this modification, or the same file used for same size DDR3 board but with T - topology can be used. Thanks Regards Priya 0 Kudos...
This seems to be more logical and implementable than that givein in i.Mx6 Rev2.5 checklist for a fly by topology. I am of the view that i.Mx6 Rev2.5 recommendations are more suited to Tree-topology and also works well when DDR3 chips are mounted on both sides of the board. Please ...
It is not necessarily for IMX6 processors but since DDR3 design is standard, can I use the recommendation from there. This seems to be more logical and implementable than that givein in i.Mx6 Rev2.5 checklist for a fly by topology. I am of the view that i.Mx6 Rev2.5 recommendations ...
This seems to be more logical and implementable than that givein in i.Mx6 Rev2.5 checklist for a fly by topology. I am of the view that i.Mx6 Rev2.5 recommendations are more suited to Tree-topology and also works well when DDR3 chips are mounted on both sides of the board. Please ...