NUZMkBWNP+EYPV47jK4XS+9Mt5pZCfdRB43+vlTspe1T5jeHz5Vr6ajkfe0yiWKUH2+HG1JJ4UuZ8VYEhSs3sG3Nq5LaagXsNeNrRNGLao21HpqL5WYTaszaIQe/634wUkUtQdSaW9C3kxCSc23j9GLGyge3m0iTTyE8KcsRxeSgpY5qIkObuE8O+tuXKRGFPJVhhTR/Nqr5f+Y/Ltsvt2/vXtftxmcKcnCv/0q8qaJjKiKToNzPfQ8yaiK5kPKxpWUlMzlFCdh+...
• FPU traps are enabled for one of the asserted PSW[31:26] bits, via the corresponding FPU_TRAP_CON.FxE bit being set. • The FPU_TRAP_CON.TST CSFR bit is clear - no previous FPU trap has been generated without the subsequent clearing of FPU_TRAP_CON.TST. Workaround The UPDFL...