Write-buffer FIFO architecture with random access snooping capabilityJames R Magro
7.1.2. Write Data FIFO Buffer The write data FIFO buffer accepts write data from the Avalon® -MM interface. The AFI controls the subsequent consumption of the FIFO buffer write data. 7.1.1. Avalon® -MM Slave Interface 7.1.3. Command Issuing FSM Company...
A distributed digital imaging processing system having a number of processing units and circular FIFO buffers connected together using data transforming streams. Processing units read data from buffers using a transforming read streams. These read streams reorder the buffer data to form patches representin...
在一个实施例中,用于流水线处理器(DSP)的跟踪缓冲器电路可以包括在写操作时按先-进先-出(FIFO)寄存器操作和在读操作时按后进-先出(LIFO)操作的互联寄存器的串联. The trace buffer circuit in one embodiment, for a pipeline processor (DSP) may be included in the write operation by the first - in, ...
In one embodiment, a trace buffer circuit for use with a pipelined digital signal processor (DSP) may include a series of interconnected registers that operate as a first-in first-out (FIFO) register on a write operation and a last-in first-out (LIFO) register on a read operation. On ...
United States Patent US7155570 Note: If you have problems viewing the PDF, please make sure you have the latest version ofAdobe Acrobat. Back to full text
In one embodiment, a trace buffer circuit for use with a pipelined digital signal processor (DSP) may include a series of interconnected registers that operate as a first-in first-out (FIFO) register on a write operation and a last-in first-out (LIFO) register on a read operation. On ...
PURPOSE:To easily constitute an FIFO buffer which can input asynchronously a write clock and a read clock by writing successively data in a data latch, and subsequently, reading it out successively. CONSTITUTION:A write address counter 1 issues a write address which is incremented by a write ...
FIFO buffer that can read and/or write multiple and /or selectable number of data words per bus cycleEhmann Gregory E
PURPOSE:To simplify circuit configuration by supplying a specified address bit signal on an address line, with designates a FIFO buffer, to the partial data input terminal of the FIFO buffer and simultaneously writing data into the FIFO buffer. CONSTITUTION:CPU 12 prepares write data for the FIFO...