"[Project 1-486] Could not resolve non-primitive black box cell 'fifo_generator_0' instantiated as 'U0/my_instance_name'" ["c:/my_top_fifo/my_top_fifo.srcs/sources_1/ipshared/test/my_fifo_v1_0/my_fifo.vhd":68][Opt 31-30] Blackbox design_1_i/my_fifo_0/U0/my_instance_name...
Hi all, When trying to compile the fifo_generator_v13_2_vhsyn_rfs.vhd library using Cadence Xcelium tool, I have the following error: xmvhdl_p: *E,ERRIPR: error within protected source code. I am using Xcelium 20.03-s008 and have launched the following c...
When using the FIFO generator to create a common-clock FIFO there is no option for selecting the operating frequency. The resulting out-of-context FIFO defaults to a 10ns/100MHz clock (shows up in the ...ooc.xdc, as well as the ...vhd) whereas my...