A semiconductor configuration includes a semiconductor body with a first connection zone of a first conductivity type, a second connection zone of the first conductivity type, a channel zone of the first conductivity type, and at least one control electrode surrounded by an insulation layer. The ...
semiconductor relay terminals in five representative fusion in a single semiconductor body with a pair of transistors (13, dmos(14) in a common collector configuration with a pair of parallel thyristor junction to opposite poles (16, 17).this relay is combined with a special control circuit to ...
The configuration of interest consists in ... Freund,P H. - 《Physical Review E》 被引量: 39发表: 1995年 Experimental verification of a self-consistent theory of the first-, second-, and third-order (non)linear optical response We show that a combination of linear absorption spectroscopy, ...
► The immunosensors have a field effect transistor configuration and... Justino C.I.L,Freitas A.C,Amaral J.P,... - 《Talanta》 被引量: 24发表: 2013年 Real time protein recognition in a liquid-gated carbon nanotube field-effect transistor modified with aptamers The combination of ...
The structural configuration of an improved submicron metal- oxide semiconductor field-effect transistor and the method of its fabrication are disclosed. A field oxidation procedure is employed to increase the thickness of the gate oxide... G Hong,CC Hsu - US 被引量: 36发表: 1996年 ...
In this study, multilayer MoS2field-effect transistors (FETs) with a back-gated configuration were fabricated on high-κAl2O3coated Si substrates. ... T Li,B Wan,G Du,... - 《Aip Advances》 被引量: 8发表: 2015年 Two- and four-probe field-effect and Hall mobilities in transition met...
Interconnected induced channel transistors of annular configuration may alternatively be used. In other arrangements suitably interconnected field-effect transistors are formed by diffusion into separate monocrystalline semiconductor islands insulated by an oxide layer from a polycrystalline substrate. The basis ...
In the first configuration example, an N-channel type MOS (metal oxide semiconductor) field-effect transistor N1, a diode bridge DB, resistors R1 to R6, capacitors C1 to C3, diodes D1 and D2, a Zener diode ZD1, and coils L1... A Sawada 被引量: 1发表: 2014年 Reducing device stress...
the drain is dispersed and attenuated in the thickness direction of the high density layers 12 and 7S, and the dielectric breakdown of the semiinsulating substrate 1 can be prevented by reducing the electrostatic concentration due to the influence of configuration effect of the high density layer....
(l < 100 nm) regions near the contacts were not covered by the top gate and thus were affected by the bottom one only. This configuration allowed us to define a lateral tunnel junction between single- and double-gated regions when the top and bottom gate voltages (VtgandVbg, ...