Thanks for your response. Yes, I have created a new zynq ps instance and configured ddr pll (fclk_clk0) and iopll (fclk_clk1) in the clock configurations tab of ZYNQ PS in vivado suit. Both are configured at 100M. (Please see the screenshot). Using these two clocks, I a...
这次测试基于CR 1T GDM-Disable,镁光颗粒需要把ClkDrv设为60.0ohm才能稳定CR1 GDM-Disable开机。