PROOFS: A fast, memory-efficient sequential circuit fault simulator - NIERMANN, CHENG, et al. - 1992 () Citation Context ... Fig. 5. The ATPG system amounts to about 1,000 lines of C code that interact with an in-house developed Fault Simulator (about 3,000 lines of code) based on...
内容提示: D A T A S H E E Twww.mentor.comSilicon Test and Yield AnalysisTessent FastScan Advanced Automatic Test Pattern GenerationIndustry Leading ATPGMentor Graphics Tessent ™ FastScan ™ is an automatic test pattern generation (ATPG) solution with a wide range of fault models, ...
It should be noted that for RTL input, the sequential mapping is performed to produce the FF's. Thereafter, it is determined whether there are no additional FF cells at step 1201. If it is determined at step 1202 that there are no additional FF cells, then the procedure is terminated ...
These tools are a sequential, partial-scan automatic test pattern generator (ATPG) and an ATPG optimized for full-scan designs. Some customer results with these tools are presented as well.PuliniG.HamacherS.Design Automation Conference, 1993, with EURO-VHDL '93. Proceedings EURO-DAC '93., ...
A two phase compaction scheme is proposed to further improve the compaction level achieved by the restoration based compaction.; Based on fast static compaction techniques, a new property based ATPG system for synchronous sequential circuits is developed. It uses fast static compaction, test sequence ...
Our algorithm analyzes different characteristics of mandatory assignments during the ATPG process. New theoretical results based on the analysis are presented which lead to significant performance improvements. The fast run time and the excellent scaling to large problems make our Boolean optimization ...