The "Resource Utilization for AXI Quad SPI v3.2" still shows results with s_AXI4_aclk clock at 100Mhz and ext_spi_clk at 50Mhz, clearly contradicting the information on AXI Quad SPI V3.2 PG153, page 15. I have a "standard mode" master SPI design that meets timing, and seems to run...