Protection in CMOS Integrated Circuits 静电放电(Electrostatic Discharge, ESD) 是造成大多数的电子元件或电子系统受到过度电性应 力(Electrical Overstress EOS) 破坏的主要因素.这种破坏会导致半导体元件以及电脑系统等, 形成一种永久性的毁坏,因而影响集成电路(Integrated Circuits, ICs) 的电路功能,而使得电...
ESD (Electrostatic Discharge) Protection in CMOS Integrated Circuits 静电放电(Electrostatic Discharge, ESD) 是造成大多数的电子元件或电子系统受到过度电性应力(Electrical Overstress EOS) 破坏的主要因素。这种破坏会导致半导体元件以及电脑系统等,形成一种永久性的毁坏,因而影响集成电路(Integrated Circuits, ICs) 的...
Robust and novel devices called High Holding, Low-Voltage-Trigger Silicon Controlled Rectifiers (HH-LVTSCRs) for Electrostatic Discharge (ESD) protection of integrated circuits (ICs) are designed, fabricated and characterized. The S-type current-voltage (I-V) characteristics of the HH-LVTSCRs are ...
ESD protection of CMOS SOI ICs is especially difficult for a number of reasons [1]. First, since devices are built on the silicon thin film, the ESD techniques based on thick-field oxide devices are not feasible. Second, due to the existence of the buried oxide in SOI, the ESD power ...
3]。完整的ESD保护应该是对整个芯片的保护，关键点是在芯片上每一个pin脚与其他任一pin脚之间创建一条有效的泄放通道。功率集成中的ESD保护分为低压保护、高压保护和接口电路的保护，本节将通过这三个方面一一阐述功率集成中ESD保护的基本内容与设计方法。[1]ESD Protection in CMOS Integrated Circuits ...
ESD(ElectrostaticDischarge)ProtectioninCMOSIntegrated Circuits 静电放电(ElectrostaticDischarge,ESD)是造成大多数的电子组件或电子系统受到过度 电性应力(ElectricalOverstress,EOS)破坏的主要因素。这种破坏会导致半导体组件以及计 算机系统等,形成一种永久性的毁坏,因而影响集成电路(IntegratedCircuits,ICs)的电路功 ...
ESD protection circuits for advanced CMOS technologies Electrostatic Discharge (ESD) has become one of the most critical reliability issues in integrated circuits (ICs). In this dissertation, a variety of ESD i... J. Chun - 《Dissertation Abstracts International》 被引量: 36发表: 2006年 Charged...
Electrostatic discharge (ESD) protection design is challenging for RF integrated circuits (ICs) because of the trade-off between the ESD robustness and parasitic capacitance. ESD protection devices are fabricated using the 0.18-μm RF CMOS process and their RF ESD characteristics are investigated by ...
Moving towards 0V ESD protectionrequires in-depth knowledge of the ESD events that could hit the I/O internal pins during bonding. For ‘standard’ monolithic ICs, ESD protection is relatively well understood. But forinternal I/O interfacesin 2.5D/3D technologies, the impact of ESD events is...
Novel circuit design techniques are presented for improving the performance of RC-triggered rail clamps for ESD protection in CMOS ICs. For system-level (powered) protection, the narrow margin between the RC-trigger and breakdown voltages of the clamp may render conventional design methods unfeasible...