【Modelsim常见问题】Error: (vsim-3170) Could not find 这个错误发生的原因通常是测试的tb文件模块名和文件名不一致导致,参考如下:
# ** Error: (vsim-3170) Could not find 'lab1_tb'. 这是因为 testbench文件名与其中module后紧跟的名称不匹配: 这里我的testbench文件名是tab1_tb, 但仿真模块里面却是logic_gates_tb, 将仿真模块里面的logic_gates_tb改为lab1_tb就可以了。
**Error: (vsim-3170) Could not find '……simulation/modelsim/rtl_work.adder8_vhd_tst'. 问题描述 从我的电脑查看文件夹……simulation/modelsim/rtl_work,发现了h_ad... 查看原文 QUARTUS15.0和MODELSIM联合仿真 bench文件,而后进行编译后可以在工作目录下的simultation-modelsim目录文件夹中找到对应后缀为vht...
**Error: (vsim-3170) Could not find '……simulation/modelsim/rtl_work.HEX4_tb'.Error loading...
When I run the simulation , the two files compile but I get the error: ** Error: (vsim-3170) Could not find 'C:\FPGA\DDS\work. '. But in the work folder there are the .dbs , .dat files (output of the compile process). Any hint on what could be...
【Modelsim常见问题】Error: (vsim-3170) Could not find**Error: (vsim-3170) Could not find '……simulation/modelsim/rtl_work.HEX4_tb'.Error loading design 小梅哥 2020-02-13 20:18:14 modelsim和Quartus使用问题 returned success but vsim could not find a design to simulate!. Please contact ...
I am using altera quartus lite 16.0 version. During simulation in the wave editor i am getting this Error message " ** Error: (vsim-3170) Could not find 'C:/altera_lite/16.0/quartus/bin64/new/simulation/qsim/work.fulladdt_b_vlg_vec_tst'.# ...
我今天刚刚解决了这个问题 我的问题在于我的工程文件建在了e盘，而我的软件装在了c盘，当我把工程文件重新建立在安装软件时的那个c盘的文件夹时，就不会报错了
# ** Error: Could not find 'E:\fpga\FPGA_example\simulation\modelsim\rtl_work.test_fifo'.在做verilog仿真时候,出现了如下的错误,而没有结果,求大师指教# ** Error: (vsim-3170) Could not find 'E:\fpga\FPGA_example\simulation\modelsim\rtl_work.test_fifo'. 相关知识点: 试题来源: 解析 Mo...
**Error: (vsim-3170) Could not find '……simulation/modelsim/rtl_work.HEX4_tb'.Errorloadingdesign 小梅哥2020-02-13 20:18:14 怎么在modelsim6.5中模拟Spartan3AN的项目 /src/unisims/primitive/SPI_ACCESS.vhd(1860): Vopt Compiler exiting#ErrorloadingdesignCan someone help?