Based on your reply, it seems like the PLL clock configuration has been unsuccessful, then after a reset and reboot, it gets stuck in PLL clock configuration again, followed by a reset and reboot, and on and on and on and on and on and on and on and on and on and on and on and...
L-Tile/H-Tile Transcever ATX PLL Intel Sttratix 10 FPGA IP used by PLL. The configured parameters are as shown in the figure below: But during the FIT stage there will be an error as shown below: My PHY is using L-Tile/H-Tile Transcever Native PHY Intel Stratix 10FPGA IP,set ...
(any Pin in the 3.0v Bank 6A, 6C, 7A or 7C),I/O Standard is selected 3.0-V LVCOMS(or 3.0-V LVTTL ) The project is compiled successfully When downloading the sof file to 9%, the following error occurs Device has stopped receiving configuration data Error message rec...
29754 - 9.2i sp3 Map - ERROR:PhysDesignRules:1701 - Unsupported configuration for PLL_ADV comp u_analog_L015/u_PG18A1/U2_pll312m/PLL_ADV_INST Description The customer connects DCM_ADV to PLL_ADV. The error appears when the PLL_ADV CLKFBIN input pin being driven by the CLKFBDCM pin. ...
Based on your reply, it seems like the PLL clock configuration has been unsuccessful, then after a reset and reboot, it gets stuck in PLL clock configuration again, followed by a reset and reboot, and on and on and on and on and on and on and on and on and on and on and on and...
So turns out if I use an external clock for my IOPLL the problem is resolved. Dotted line is the configuration in the project above resulting in the error, solid line for userclk (reference to IOPLL) from another FPGA pin works fine: View solution in origina...
"Error (16021): You specified a configuration mode that includes memory initialization, however memory initialization is not supported by the selected device. In the Device and Pin Options dialog box, choose a configuration mode without memory initialization." I attempted to address this issue by ma...
So turns out if I use an external clock for my IOPLL the problem is resolved. Dotted line is the configuration in the project above resulting in the error, solid line for userclk (reference to IOPLL) from another FPGA pin works fine: View solution ...
So turns out if I use an external clock for my IOPLL the problem is resolved. Dotted line is the configuration in the project above resulting in the error, solid line for userclk (reference to IOPLL) from another FPGA pin works fine: 翻译 ...
29754 - 9.2i sp3 Map - ERROR:PhysDesignRules:1701 - Unsupported configuration for PLL_ADV comp u_analog_L015/u_PG18A1/U2_pll312m/PLL_ADV_INST Description The customer connects DCM_ADV to PLL_ADV. The error appears when the PLL_ADV CLKFBIN input pin being driven by the CLKFB...