Error (10149): Verilog HDL Declaration error at core_debug.sv(1): identifier "seq_core_debug_pkg" is already declared in the present scopeEnvironment Bug ID: 1408013834 Quartus Edition Quartus® II Subscription Edition Version Found: 12.1 Version Fixed: 13.0 Descriptio...
描述错误:标示符‘clk1’已被声明。可以换个变量
The problem is due to the core_debug.sv file being listed twice in the design example .qip file. Resolution The workaround is to comment out one of the files in the design example .qip file. For example : #set_global_assignment -library "<IP_name>_example" -name SYSTEMVERILOG_FILE [...