[0059] (3) The equalization parameter S1301 corresponding to the counter value obtained in the above (2) is set as an optimum equalization parameter for a transmitting circuit which is paired with the receiving circuit 123 and disposed on the same PKG where the receiving circuit 123 is dispose...
(d3) counting a result during a predetermined number of symbol terms and outputting the counted value as an SER when said training sequence is not identical to said reference signal in said step (d1). 3. An equalizing method as claimed in claim 1, wherein said predetermined algorithm is ...
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3. The equalizer defined in claim 2 further comprising: fourth analog adder means having a first input connected to the output of said first analog adder, and gate means having an input connected to the output of said first analog adder and an output connected to a second input of said...
3 to output, during a given transmit interval, a primary signal and corresponding equalization signal onto signal path 122. The transceiver also includes a sampling circuit 123, buffer circuit 132, tap selector 156 and tap select logic 157. The sampling circuit 123 samples data signals ...