reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;phy-reset-duration = <1>;fsl,magic-packet;status = "okay";mdio {#address-cells = <1>;#size-cells = <0>;ethphy0: ethernet-phy@1 {compatible = "ethernet-phy-ieee802.3-c22";reg = <1>;vddio-supply = <&vddio>;vddio: ...
ENET_REF_CLK is the input pin for RGMII reference clock, so if you want to use GPIO_16 to provide the 125M clock, you should connect GPIO_16 to ENENT_REF_CLK, and be careful, the voltage level might be different, you might need an level shift. 0 Kudos Reply 04-11-2016 01...
CLK_DEBUG(printf("ARM clock frequency: %9d HZ\n", clk_get_freq(arm_clk)));/* initialise the eFuse controller so we can get a MAC address */ocotp = ocotp_init();/* Initialise ethernet pins */gpio_init();setup_iomux_enet();/* Initialise the phy library */miiphy_init();/* In...
reg = *((unsigned int*)(GPIO1_BASE_ADDR + 0x00)); reg &= ~0x2000000; *((unsigned int*)(GPIO1_BASE_ADDR + 0x00)) = reg; while(i--) ; reg = *((unsigned int*)(GPIO1_BASE_ADDR + 0x00)); reg |= ~0x2000000; *((unsigned int*)(GPIO1_BASE_ADDR + 0x00)) = reg; } ...
/* Enable GPIO5 Ethernet Pins, drive MII clock 25MHz. */ GPIO5->DDR |= 0x0C; GPIO5->DR[0x0C<<2] = 0x00; SCU->GPIOTYPE[5] &= ~0x0C; SCU->GPIOIN[5] &= ~0x0C; SCU->GPIOOUT[5] &= ~0x00F0; SCU->GPIOOUT[5] |= 0x00A0; ...
$(path_hm_d1)/halmac_gpio_88xx$(v1).o \ $(path_hm_d1)/halmac_init_88xx$(v1).o \ $(path_hm_d1)/halmac_mimo_88xx$(v1).o halmac-$(pci) += $(path_hm_d1)/halmac_pcie_88xx$(v1).o halmac-$(sdio) += $(path_hm_d1)/halmac_sdio_88xx$(v1).o hal...
215 /*MX8MQ_IOMUXC_ENET_TD2_GPIO1_IO19 0x19 Set as gpio to test hardware!!!*/216 MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x56217 MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x56218 MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x56219 MX8MQ_IOMUXC_ENET_RD0_ENET...
You said "The 125M reference clock could be from PHY chip, or external oscillator, and could also be routed from GPIO_16(need software configuration)." I want to ask how to routed from GPIO_16?What is the detail configuration? Now I can generate the 125M clock at the GPIO_16. Thank...
You said "The 125M reference clock could be from PHY chip, or external oscillator, and could also be routed from GPIO_16(need software configuration)." I want to ask how to routed from GPIO_16?What is the detail configuration? Now I can generate the 125M clock at the GPIO_16...
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;phy-reset-duration = <1>;fsl,magic-packet;status = "okay";mdio {#address-cells = <1>;#size-cells = <0>;ethphy0: ethernet-phy@1 {compatible = "ethernet-phy-ieee802.3-c22";reg = <1>;vddio-supply = <&...