fpga bitstream needs to be listed in config node in FIT image. Only tested option is bitstream in BIN format. Enabling this feature increase code size by almost 4k. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Series-to: uboot Cover-letter: arm64: zynqmp: Enable loading FPGA ...
uint32_t __weak spl_nand_get_uboot_raw_page(void) { #ifdef CONFIG_SYS_NAND_U_BOOT_OFFS return CONFIG_SYS_NAND_U_BOOT_OFFS; #else return 0; #endif } #if defined(CONFIG_SPL_NAND_RAW_ONLY) 0 comments on commit 421b721 Please sign in to comment. Footer...
u-boot,spl-boot-order = \ "same-as-spl", &emmc, &sdmmc; }; }; &dmc { u-boot,dm-pre-reloc; }; 2 changes: 1 addition & 1 deletion 2 arch/arm/mach-rockchip/Makefile Original file line numberDiff line numberDiff line change @@ -17,7 +17,7 @@ obj-tpl-$(CONFIG_ROCKCHIP...
frank-w / u-boot Public Notifications Fork 22 Star 55 Commit Permalink Refactor IMAGE_ENABLE_VERIFY to handle builds without SPL verification Browse files If building with SPL_LOAD_FIT_FULL and FIT_SIGNATURE, but without SPL_FIT_SIGNATURE then the build fails with: common/built-in.o:...
Write two files to the NAND device as follows: - spl/u-boot-spl.bin at the offset address 0x00000000 - u-boot-dtb.img at the offset address 0x00010000 - spl/u-boot-spl-dtb.bin at the offset address 0x00000000 - u-boot-dtb.img at the offset address 0x00010000 If a TFTP server is...
CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -27,6 +29,9 @@ CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set CONFIG_USE_BOOTCOMMAND=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_SPL_SIZE_LIMIT_SUBTRACT_GD=y CONFIG_SPL_SIZE_LIMIT_SUBTRACT_MALLOC=y CONFIG_SPL_SYS_REPORT_STACK_...
SPL_SYS_MALLOC_SIMPLE can be disabled only by setting SPL_SYS_MALLOC_F_LEN to zero. So do it. This change fixes SPL error "alloc space exhausted" on P2020 board. Signed-off-by: Pali Rohár <pali@kernel.org>Loading branch information ...
u-boot / u-boot Public Notifications Fork 3.7k Star 4.1k Commit Permalink drivers: video: tidss: Kconfig: Configs to enable TIDSS at SPL Browse files To enable tidss display driver only at SPL stage, add necessary config, CONFIG_SPL_VIDEO_TIDSS. Signed-off-by: Nikhil M Jain ...
@@ -226,7 +226,6 @@ config SPL_MULTI_DTB_FIT_USER_DEF_ADDR config OF_SPL_REMOVE_PROPS string "List of device tree properties to drop for SPL" depends on SPL_OF_CONTROL default "interrupt-parent" if SPL_PINCTRL && SPL_CLK default "clocks clock-names interrupt-parent" if SPL_PINCTRL...
+ u-boot,dm-spl; + rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>; + }; + + }; }; + diff --git a/configs/blade3_defconfig b/configs/blade3_defconfig index 0ed3a08d853..07dde02b427 100644 --- a/configs/blade3_defconfig +++ b/configs/blade3_defconfig @@ -6,...