RMII works with 2-bit data at 50MHz clock. PHY (like TJA1103) usually works in rev-RMII mode, where PHY generates REF_CLK for MAC (S32K3/EMAC_MII_RMII_TX_CLK). RMII does not use external signal RX_CLK as can be seen on lwip examples. The trick is that the EMAC processing data...
对于 RMII 模式，如果 REF_CLK 没有时钟，则会卡住。检查 REF_CLK 时钟是否异常： 先检查 REF_...
I've verified that I have a 50MHz input clock on E_REF_CLK, and the value of LPC_RGU->RESET_STATUS1 (page 198 manual) all '01's except for ETHERNET_RST which is '11' - this tells me that the EMAC received the RGU reset. Is there any setup step or input...
no mdio control * - "<bus>:<addr>" : use the specified bus and phy */ const char *phy_id; u8 rmii_en; u8 version; bool no_bd_ram; void (*interrupt_enable) (void); void (*interrupt_disable) (void); }; enum { EMAC_VERSION_1, /* DM644x */ EMAC_VERSIO...
RMII works with 2-bit data at 50MHz clock. PHY (like TJA1103) usually works in rev-RMII mode, where PHY generates REF_CLK for MAC (S32K3/EMAC_MII_RMII_TX_CLK). RMII does not use external signal RX_CLK as can be seen on lwip examples. The trick is that the EMAC ...
解決済み: Hi, NXP When using the RMII mode of the EMAC module in S32K3x4, why is it necessary to configure MII_RX_CLK to 25MHz? If configured to 50MHz,
RMII works with 2-bit data at 50MHz clock. PHY (like TJA1103) usually works in rev-RMII mode, where PHY generates REF_CLK for MAC (S32K3/EMAC_MII_RMII_TX_CLK). RMII does not use external signal RX_CLK as can be seen on lwip examples. The trick is that the EMAC pro...
I've verified that I have a 50MHz input clock on E_REF_CLK, and the value of LPC_RGU->RESET_STATUS1 (page 198 manual) all '01's except for ETHERNET_RST which is '11' - this tells me that the EMAC received the RGU reset. Is there any setup step or input condition ...