Tdutycycle_ext Clock duty cycle, REF_CLK sourced by external clock source 35 50 65 % Table 77. RMII TX Timing Requirements For specification status, see the Data Sheet Status table SymbolDescriptionMinTypMaxUnit Td TX_CLK to TXD/TX_CTL output data delay 2 — 10 ns Figure 13. RMII T...
Then i modified the phy-mode to 'rmii' and 'mii' respectively accroding to the hardware configuration. But i know that the fixed-link property is not support in the uboot by default. So for now, i just want to get the cpsw_emac1 to...
I've verified that I have a 50MHz input clock on E_REF_CLK, and the value of LPC_RGU->RESET_STATUS1 (page 198 manual) all '01's except for ETHERNET_RST which is '11' - this tells me that the EMAC received the RGU reset. Is there any setup step or input...
I've verified that I have a 50MHz input clock on E_REF_CLK, and the value of LPC_RGU->RESET_STATUS1 (page 198 manual) all '01's except for ETHERNET_RST which is '11' - this tells me that the EMAC received the RGU reset. Is there any setup step or input...
I've verified that I have a 50MHz input clock on E_REF_CLK, and the value of LPC_RGU->RESET_STATUS1 (page 198 manual) all '01's except for ETHERNET_RST which is '11' - this tells me that the EMAC received the RGU reset. Is there any setup step or input condition ...