12. A master device must internally provide a hold time of al least 300 ns for the SDA signal (refer to VIL of the SCL signal) in order to bridge the undefined region SCL’s falling edge. 13. The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall...
Time (VDD = 4.5 V to 5.5 V) (VDD = 2.3 V to 4.5 V) (VDD = 1.65 V to 2.3 V) tSU(D) Data Input Setup Time 100 100 100 ns tH(D) Data Input Hold Time 1 1 1 ms INTERRUPT TIMING: CL v 100 pF (See Figures 9 and 10) tV(INT_N) tRST(INT_N) Data Valid Time 4 4 4 ...