so presumably this requirement is the same for all other Rockchip SoCs using this IP. Add the necessary code to double the clock frequency when 8-bit DDR is selected. The dw_mmc core already handles setting CLKDIV correctly given the input clock and desired bus clock. Signed-off-by: John...
@@ -159,6 +159,10 @@ static int rockchip_dwmmc_probe(struct udevice *dev)host->mmc->dev = dev;upriv->mmc = host->mmc;/* Hosts capable of 8-bit can also do 4 bits */if (host->buswidth == 8)plat->cfg.host_caps |= MMC_MODE_4BIT;return...
mmc: dw_mmc-rockchip: dt-binding: Add tuning related things mmc: dw_mmc: Generic MMC tuning with the clock phase framework ARM: dts: rockchip: Add drive/sample clocks for rk3288 dw_mmc devices Douglas Anderson (4): clk: rockchip: Allow more precision for some mmc clock phases clk: r...
static int dw_mci_rockchip_init(struct dw_mci *host) @@ -95,6 +255,8 @@ static const struct dw_mci_drv_data rk3288_drv_data = { .caps = dw_mci_rk3288_dwmmc_caps, .prepare_command = dw_mci_rockchip_prepare_command, .set_ios = dw_mci_rk3288_set_ios, + .execute_tuning =...
In dw_mmc.c, it's enabled by default. It doesn't need to set MMC_CAP_ERASE in rockchip anymore. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> ...
Use 0 as the return value when setting clock rate fails, the mmc core will configure to use bypass mode instead of using a bogus divider. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>...
vqmmc but not the vmmc regulator is supplied. > - add Acks from Jaehoon Chung to the dw_mmc parts > - drop first two clock patches that already got applied to the mmc tree > > changes since v1: > - address comment from Jaehoon Chung and keep this local to Rockchip > for the ...
Signed-off-by: Alexandru M Stan <ams...@chromium.org> Signed-off-by: Heiko Stuebner <he...@sntech.de> Acked-by: Jaehoon Chung <jh80.ch...@samsung.com> --- Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.txt | 13 ++++++++ 1 file changed, 13 insertions(+) diff --git...
+* rockchip,default-sample-phase: The default phase to set ciu_sample at + probing, low speeds or in case where all phases work at tuning time. + If not specified 0 deg will be used. + Example: rkdwmmc0@12200000 { -- 2.5.1 ...
[PATCH v3 6/7] ARM: dts: rockchip: Add drive/sample clocks for rk3288 dw_mmc devices From: Alexandru M Stan <ams...@chromium.org> The drive/sample clocks can be phase shifted. The drive clock could be used in a future patch to adjust hold times. The sample...