/* Bit fields in CTRLR0 based on DWC_ssi_databook.pdf v1.01a */ #defineDWC_SSI_CTRLR0_SRL_OFFSET13 #defineDWC_SSI_CTRLR0_TMOD_OFFSET10 #defineDWC_SSI_CTRLR0_TMOD_MASKGENMASK(11, 10) #defineDWC_SSI_CTRLR0_SCPOL_OFFSET9 #defineDWC_SSI_CTRLR0_SCPH_OFFSET8 ...