The Synopsys Designware Ethernet QOS IP block with specific 234+ configuration used in Rockchip SoCs. 235+ 228236 config DWC_ETH_QOS_STM32 229237 bool "Synopsys DWC Ethernet QOS device support for STM32" 230238
#include "dwc_eth_qos.h"/* Core registers */#define EQOS_MAC_REGS_BASE 0x000 struct eqos_mac_regs { uint32_t configuration; /* 0x000 */ uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */ uint32_t q0_tx_flow_ctrl; /* 0x070 */ ...
data = (ulong)&eqos_stm32_config 2031 }, 2032#endif 2033#if IS_ENABLED(CONFIG_DWC_ETH_QOS_IMX) 2034 { 2035 .compatible = "fsl,imx-eqos", 2036 .data = (ulong)&eqos_imx_config 2037 }, 2038#endif 2039 2040 { } 2041}; 2042 2043U_BOOT_DRIVER(eth_eqos) = { 2044 .name = "...
12 changes: 6 additions & 6 deletions 12 drivers/net/dwc_eth_qos.c Original file line numberDiff line numberDiff line change @@ -621,7 +621,7 @@ static int eqos_start_clks_stm32(struct udevice *dev) return ret; } void eqos_stop_clks_tegra186(struct udevice *dev) static void ...
16 changes: 3 additions & 13 deletions 16 drivers/net/dwc_eth_qos.c Original file line numberDiff line numberDiff line change @@ -1591,8 +1591,8 @@ static int eqos_probe_resources_tegra186(struct udevice *dev) } /* board-specific Ethernet Interface initializations. */ __weak int boa...