static void dmub_replay_enable(struct dmub_replay *dmub, bool enable, bool wait, uint8_t panel_inst) { union dmub_rb_cmd cmd; struct dc_context *dc = dmub->ctx; uint32_t retry_count; enum replay_state state = REPLAY_STATE_0; memset(&cmd, 0, sizeof(cmd)); cmd.replay_enable...
> drm_panel *panel, > panel_bridge->bridge.ops = DRM_BRIDGE_OP_MODES; > panel_bridge->bridge.type = connector_type; > > - panel_bridge->bridge.pre_enable_upstream_first = > + panel_bridge->bridge.pre_enable_prev_first = > panel->prepare_upstream_first; > > drm_bridge_add(&panel...
+++ b/include/drm/display/drm_dp.h @@ -743,6 +743,7 @@ # define DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN (1 << 4) # define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN (1 << 5) # define DP_PANEL_REPLAY_SU_ENABLE (1 << 6) +# define DP_PANEL_REPLAY_ENABLE_SU_REGION_ET (1...
eDP1.5 allows Panel Replay on eDP as well. Take this into account when enabling sink PSR/Panel Replay. Write also PANEL_REPLAY_CONFIG2 register accordingly. Signed-off-by: Jouni Högander <jouni.hogan...@intel.com> --- drivers/gpu/drm/i915/display/intel_psr.c | 63 ++++++++++---...
+++ b/include/drm/display/drm_dp.h @@ -743,6 +743,7 @@ # define DP_PANEL_REPLAY_RFB_STORAGE_ERROR_EN (1 << 4) # define DP_PANEL_REPLAY_ACTIVE_FRAME_CRC_ERROR_EN (1 << 5) # define DP_PANEL_REPLAY_SU_ENABLE (1 << 6) ...
+ panel_replay_config2); } static void _psr_enable_sink(struct intel_dp *intel_dp, @@ -748,15 +756,31 @@ static void _psr_enable_sink(struct intel_dp *intel_dp, drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, val); ...