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The data is presented in 2's-complement form (MSB-first) and is valid on the rising edge of bit clock. 8.3.2.1.2 Left-Justified Left-justified (LJ) timing also uses LRCK to define when the data being transmitted is for the left channel and when it is for the right channel. LRCK ...
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When the last word transfers, the master generates a STOP condition to release the bus. A generic data transfer sequence is shown in Figure 44. 8.4.2.5.3 Writing to the I²C Control Port As shown in Figure 45, a single-byte data-write transfer begins with the master device transmitting...