下面图中的DRC LUTLP-1的loop错误是设计可接受的的。 且对仿真结果不影响,综合实现都通过,到生成bitstream时出现DRC错误,根据xilinx官方社区的帮助,解决了这问题。 在生成bitstream之前,进行设置。 在bitstream设置界面的tcl.pre出添加一个tcl文件,文件中包含“set_property SEVERITY {Warning} [get_drc_checks LUTLP-...
生成bit错误:[DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this ...
@msh，组合循环是组合逻辑，无需寄存器即可反馈给自身。最简单的例子是一个逆变器，其输出反馈到输入端...
生成bit错误:[DRC LUTLP-1] Combinatorial Loop Alert: 1 LUT cells form a combinatorial loop. This can create a race condition. Timing analysis may not be accurate. The preferred resolution is to modify the design to remove combinatorial logic loops. If the loop is known and understood, this ...