A structure and process for making a non-aligned MOSFET structure for ESD protection using resistor wells as the diffusions and adjustable capacitors. The present invention compensates the shallow extension region without the need for additional masks. The source/drain doping is less than that of a...
Filing Date: 05/03/2005 Export Citation: Click for automatic bibliography generation Primary Class: 716/52 International Classes: G06F17/50 View Patent Images: Download PDF 20060253813 Related US Applications:20170046470 PROCESS DESIGN KIT FOR EFFICIENT AND ACCURATE MISMATCH SIMULATION OF ANALOG CIRCUITS...