一个if就要对应一个end if 或者你不想写end if 就要把else 和if连起来写成elsif,这样只要写一个end if就行了。还有一些其他错误,已改好且编译通过 LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY KUOPIN1 IS PORT(EN,CLK,SIN:IN STD_LOGIC;SIG_OUT:OUT...
Error (10818):vhdl Error (10818):Can't infer register for "a0[0]" at shiftreg.vhd(96) because it does not hold its value outside the clock edgePROCESS(clk_in,clk_5)BEGINIF clk_5'EVENT AND clk_5='1' THENa16
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Error (10818): Can't infer register for "q2_int[X]" at counter.vhd(32) because it does not hold its value outside the clock edge. for every bit, someone has an idea how to solve it? the code is: --- Quote Start --- lib...
aError (10818): Can't infer register for "count_1[0]" at try_2.vhd(163) because it does not hold its value outside the clock edge 错误(10818) : 不能推断登记“count_1 (0)”在try_2.vhd (163),因为它不表示它的价值在时钟脉冲边沿之外[translate]...
(35) because it does not hold its value outside the clock edge Info (10041): Inferred latch for "etat" at projet1.vhd(31) Error (10818): Can't infer register for "l_vert" at projet1.vhd(35) because it does not hold its value outside the clock e...