When using Vivado 2021.1 and synthesizing some HLS IP's, synthesis does not complete when using a Windows OS. Based on the synthesis logs, synthesis appears to stall when analyzing a design file: This has been seen with IPs such as the VPSS, Video Mixer, and Video Multi-Scaler in the Vi...
2014.4Vitis2014.22014.3Vivado Design Suite2013.42014.1HLS知识库Files(0) Download No records found. 关注 Preferred Language 选择一个选项 热门文章 000036274 - 自适应 SoC 与 FPGA 设计工具 - 许可解决方案中心 【译】在 Windows 10 上快速安装赛灵思平台电缆 USB II 的电缆驱动程序 000036235 - Vivado ML ...
I specifically wanted to avoid the DTG, as I stated in my original post, because to use it I need to create a dummy design without a BSP and without a PL (except for an instantiated PS), then generate an XSA, then use the DTG. It's a cumbersome process,...