3) two-to-one frequency divider 二比一分频器 4) clock division circuit 分频电路 1. Counter,as a typicalclock division circuit,has some advantages such as easy implement,wave even. 计数器作为一种典型分频电路有容易实现、波形均匀等优点,其遵循二分频原理也就要求在应用中系统时钟必须是输出频率整数倍...
The variable resistance element is disposed between the two differential output nodes of the latch such that appreciable DC bias current does not flow across the variable resistance element. As a consequence, good output signal voltage swing is maintained at high frequencies, and divider current ...
A novel toggled flip-flop(TFF) divide-by-two circuit(DTC) and its optimization method based on a large-signal analysis approach are proposed.By reducing the output RC constant in tracking mode and making it large in latching mode,compressing the internal signal swing as well as compensating the...
专利名称：DIVIDE-BY-TWO DIVIDER CIRCUIT HAVING BRANCHES WITH STATIC CURRENT BLOCKING CIRCUITS 发明人：KHALILI, Alireza 申请号：US2014/011181 申请日：20140111 公开号：WO2014/120416A3 公开日：20141023 专利内容由知识产权出版社提供 专利附图：摘要：A divide-by-two divider circuit receives a differential ...
Texas Instruments CDC303 112Kb / 1P [Old version datasheet] OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER CDC304 88Kb / 6P [Old version datasheet] OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER CDC304 96Kb / 6P [Old version datasheet] Octal Divide By 2 Circuit/Clock Driver CDC304D 96Kb / 6P ...
An Integrated Divide-by-Two Direct Injection-Locking Frequency Divider for Bands Through In this work, direct injection locking is applied to a ring oscillator topology to design a wideband divide-by-two frequency divider circuit with a locking... D Toso,S. - 《IEEE Transactions on Microwave Th...
专利名称:Divide-by-two frequency divider 发明人:Marc Rocchi 申请号:US06/622351 申请日:1984 0619 公开号:US04 623801A 公开日:19861118 摘要:An integrated divide-by-two frequency divider circuit in BFL logic of the masterslave flip-flop type which comprises two complementary outputs Q and Q and...
The first ILRO includes a pair of cross-coupled N-channel transistors, a pair of load resistors, capacitors and current injection circuit integration. 每一晶体管的漏极耦合到另一晶体管的栅极. The drain of each transistor is coupled to the gate of the other transistor. 每一负载电阻器将每一...
Divide-by-two injection-locked ring oscillator circuit 发明人: FAGG RUSSELL J. 申请人: 申请日期: 2009-09-03 申请公布日期: 2013-07-16 代理机构: 代理人: 地址: 摘要: A frequency divider involves a plurality of Injection-locked Ring Oscillators (ILRO). A first ILRO includes a pair of...
The counter divider circuit employs predetermined logic delays by buffered gating controlled by the master clock, which produces two signals. These two signals act as enable control signals such that the timing of their rising and falling edges is arranged to never propagate through the clock ...