Designing of Full Subtractor using Half-SubtractorsA Full-Subtractor can also be implemented using two half-subtractors and one OR gate. The circuit diagram for this can be drawn as,The Boolean expressions for Difference and Borrow are,
In this paper, a new architecture of Half and Full subtractor based on the QCA is proposed. The benefit of optimal FNZ universal gate is taken in demonstrating these arithmetic units, which has already designed based on the QCA. The design helps to reduce the complexity, then the conventional...
Generally, the full subtractor is one of the most used andessential combinational logic circuits. It is a basic electronic device, used to perform subtraction of two binary numbers. In the earlier article, already we have given the basic theory ofhalf adder & a full adderwhich uses the binary...
The analyzed combinational logic functions are Half-Adder, Full-Adder, Half-Subtractor, and Comparator One-Bit. The operation principle of these combinational logic functions is based on the constructive and destructive interferences between the input signal(s) and control signal. Numerical simulations ...
Adder and subtractor are used widely in almost every data processing system. For efficient hardware implementation, a single hardware can be used to perform both addition as well as subtraction. In this paper, a novel majority logic based adder-subtractor architecture is proposed. The proposed ...
A novel design of 8-bit adder/subtractor by quantum-dot cellular automata. J. Comput. Syst. Sci. 80(7): 1404-1414.M. Kianpour, R. Sabbaghi-Nadooshan, and K. Navi, "A novel design of 8-bit adder/subtractor by quantum-dot cellular automata," Journal of Computer and System Sciences,...
In our design, the full adders are realized using synthesizable, less transistor count and low garbage output PRT-2 gates. Further, in our design for bias subtraction, PRT-1 gate is used as a zero subtractor and one subtractor since it has less critical path delay. Then for normalization, ...
For this reason, it was necessary to add a fifth adder/subtractor. In an RTL design, this would have resulted in a significant amount of coding to add the required resource and connect it up to the other resources in the design; however, using AAD the change was trivial – as shown in...
Hence optimization of power consumption of adder circuits is a challenging task in the recent year and is a need of today's world. In order to give a justice to this problem, work presented in this paper describes the technique of designing floating point adder and subtractor using low power...
The prediction module is composed of an adder, a subtractor, four registers, and a quantization table as shown in Figure 10. The register “pre” stores the previous reconstruction value, “diff” stores the difference between the current reconstruction value and the previous predicted reconstruction...