Anand SeshadriBob StrongUSUS5986314 * Oct 8, 1997 Nov 16, 1999 Texas Instruments Incorporated Depletion mode MOS capacitor with patterned Vt implantsUS5986314 * 1997年10月8日 1999年11月16日 Texas Instruments Incorporated Depletion mode MOS capacitor with patterned V.sub.t implants...
III-N high voltage MOS capacitors and System on Chip (SoC) solutions integrating at least one III-N MOS capacitor capable of high breakdown voltages (BV) to implement high voltage and/or high power circuits. Breakdown voltages over 4V may be achieved avoiding any need to series couple ...
Four implementations of MOSFET-2QO\ PRdu- lators for audio applications are presented using diffe- rent topologies of depletion-mode MOS-capacitors. The 2nd-order fully-differential modulators are realized in Switched-Opamp technique with DC level shift. Imple- mentation is performed in a standard...
Power MOSFETs are most often used in switched-mode applications where they function as an on-off switch. However, in applications such as start-up circuits in SMPS, surge and high voltage protection, reverse polarity protection, or solid-state relay, the
A DC-to-DC converter includes a high-side transistor and a low-side transistor wherein the high-side transistor is implemented with a high-side enhancement mode MOSFET. The low side-transistor further includes a low-side enhancement MOSFET shunted with a depletion mode transistor having a gate...
Applying a gate-to-source voltage in such a way that will make the gate negative relative to the source, the negative charge will force free electrons out of the channel. It will induce positive charges in the channel through the SiO2 of the gate capacitor – forming a carrier-depletion re...
As previously mentioned, the applied voltage determines whether the TSV operates in either the accumulation region, the depletion region, or in inversion, similar to a MOS capacitor. The ratio of the TSV capacitance to the oxide capacitance as a function of the applied voltage Vg is illustrated ...
Depletion Trench Capacitor Cell Process technologies for megabit level dynamic RAMs are presented emphasizing submicron channel length MOSFET characteristics and cell size reduction. N-well CMOS composed of 0.5m n-and 0.9m p-channel length MOSFETs are used for peripher... T Morie,K Minegishi,M ...
However, the “gain” of the MOS capacitor structure in the feedback loop dC/dV is very low for small area devices, and the SNR is very poor, thus preventing sensitive measurements. For this reason, we compared the two DLTS modes by using 400 MOSFETs connected in parallel, each of W/L...
1. A random access memory integrated circuit comprising an array of dynamic one-device memory cells wherein each cell contains an enhancement-mode FET switch and a charge storage capacitor; and circuits peripheral to the array containing both enhancement-mode FETs and depletion-mode FETs; said inte...