case(sel) 4'b0000: dout0 = din ; 4'b0001: dout1 = din ; However a better way write this code is to index into a bit vector module demux( // use Verilog-2001 syntax for your ports so you only have to declare these once, not up to 3 times...
1 libraryIEEE; 2 useIEEE.std_logic_1164.all; 3 useIEEE.std_logic_arith.all; 4 5 entityDEMUX1X16is 6 port(S:instd_logic_vector(3downto0); 7 I:instd_logic; 8 Q:outstd_logic_vector(15downto0) 9 ); 10 endentity;
Code Size: 26kCategory: VHDL-FPGA-VerilogDevelopment Platform: VHDLSMPTE372_rx_1080p_demux.v:Code Content //--- // Copyright (c) 2007 Xilinx, Inc. // All Rights Reserved //--- // ___ ___ // / // / //
case(sel) 4'b0000: dout0 = din ; 4'b0001: dout1 = din ; However a better way write this code is to index into a bit vector module demux( // use Verilog-2001 syntax for your ports so you only have to declare these once, not up to 3 times...
case(sel) 4'b0000: dout0 = din ; 4'b0001: dout1 = din ; However a better way write this code is to index into a bit vector module demux( // use Verilog-2001 syntax for your ports so you only have to declare these once, not up to 3 times input wire...
case(sel) 4'b0000: dout0 = din ; 4'b0001: dout1 = din ; However a better way write this code is to index into a bit vector module demux( // use Verilog-2001 syntax for your ports so you only have to declare these once, not up to 3 times input wire...