C. Venerus, "Delta-sigma FDC based fractional-N PLLs with multi-rate quantizing dynamic element matching," Ph.D. dissertation, Dept. Elect. Comput. Eng., Univ. California, San Diego, CA, USA, 2013.VENERUS C; GALTON I.Delta-Sigma FDC based fraction- al-N PLLS.IEEE Transactions on ...
Fractional-$N$ phase-locked looprequencyynthesizersasednime-to-digitalonverters (TDC-PLLs)aveeen proposedoeducehereand linearityequirementsfonventional PLLsasedn delta-sigmaodulationndharge pumps ($Deltaigma$ -PLLs).lthoughDC-PLLs with good performanceaveeen demonstrated,DC quantization noi...
Phase-Noise Cancellation Design Tradeoffs in Delta--Sigma Fractional-N PLLs. Pamarti, S., Galton, I.: Phase-Noise Cancellation Design Tradeoffs in Delta-Sigma Fractional-N PLLs. IEEE Transactions on Circuits and Systems II: ... Pamarti,Sudhakar,Galton,... - 《IEEE Transactions on Circuits ...
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Galton, "Delta-sigma FDC based fractional-N PLLs," IEEE Trans. Circuits Syst. I: Reg. Papers, vol. 60, no. 5, pp. 1274-1285, May 2013.C. Venerus and I. Galton, "Delta-Sigma FDC Based Fractional-N PLLs," IEEE Trans. on Circuits And Systems--I: Regular Papers, vol. 60, no...
Fractional spurPhase noiseA fractional-N phase-locked loop (PLL) with four kinds of delta-sigma modulators (DSMs), is implemented to analyze and compare PLL phase noise and fractional spur performances among different DSMs, including 4(th)- and 5(th)-order single-loop (SL) and 3(rd)- ...
A fractional-N phase-locked loop (PLL) includes a nonlinear time to digital converter that generates a digital representation of a phase error corresponding to a time difference between a feedback signal of the fractional-N PLL and a reference signal. A nonlinear quantization noise cancellation ...