网络延时周期 网络释义 1. 延时周期 有时周延,logic... ... ) undistribution 有时不周延 )delay cycle延时周期) in-sequence delay 有序延时 ... www.dictall.com|基于 1 个网页
1) delay cycle 延时周期2) Cyclic active sludge system 周期循环延时曝气法3) Periodic extension 周期延拓4) casting cycle 流延周期5) deferred cycle 延迟周期6) delay period 滞后期,延迟时期,缓发周期;滞燃期补充资料:M67式延时杀伤手榴弹 m67式延时杀伤手榴弹 概述 m67式延时杀伤手榴弹是在m33式防御...
delay n. 1.耽搁,延迟 2.被耽搁[推迟]的事件或时间 3.(电话讯息从接收到直播节目转播之间的)时间间隔装置 4.【美式橄榄球】(持球队员或准备接球队员的)停顿战术,延迟动作,假动作 cycle n. 1.循环,周期 2.自行车,摩托车 3.整套,整个系列(如机器的运转) v.[I] 1.骑自行[摩托]车,骑自行车 on delay...
cycle名— 周期名 · 循环名 · 轮回名 · 自行车名 · 一圈名 · 骑车名 · 摩托车名 · 一转名 · 一周名 · 组诗名 cycle— 周 · 旋回 cycle动— 循环动 · 骑车动 delay动— 拖延动 · 延迟动 · 延期动 · 阻延动 · 推动 ·
网络释义 1. 周期延迟 delay的翻译中文意思-在线英汉词典 ... cut-out delay 切除延迟cycle delay周期延迟data delay 数据延迟 ... www.chinabaike.com|基于4个网页 2. 循环间延迟时间 Mega Power Gemini-3020i EVO... ... Cycle time 循环次数Cycle delay循环间延迟时间Cycle direction 循环方式 ... ...
Twitter Google Share on Facebook cycle delay selector [′sī·kəl di¦lā sə′lek·tər] (computer science) An electromechanical device in a sorter which causes a cycle to be skipped so that the card out of sequence may be directed to a different pocket. ...
cycle delay 释义 见:delay: cycle delay 随便看 tilting pinch rolls tilting position tilting ring tachometer tilting roller tilting screw tilting seat tilting spout tilting stand tilting suspension tilting table tilting table stop tilting-type boxcar unloader tilting-type feed steamer tilting-type mixer ti...
Cycle delay 翻译结果4复制译文编辑译文朗读译文返回顶部 Cycle Delay 翻译结果5复制译文编辑译文朗读译文返回顶部 Circulation time delay 相关内容 aChoc genoux 正在翻译,请等待...[translate] aImportSet ImportSet[translate] ai like your affection i like your affection[translate] ...
An integrated circuit for a half cycle delay locked loop is disclosed. The integrated circuit includes an input node coupled to an oscillator having a clock cycle of M. The integrated circuit also includes N delay elements outputting N different phase-shifted signals, where a total delay ...
If rst_n is low, there is one cycle delay. If rst_n is high, there is NO one cycle delay. It seems that different version has different compiling policy. Someone told me that I can set constraints to make it work normal. I am a starter on FPGA. Can anyone help to ...