The VLSI architecture has been authored in Verilog code for fault secure encoder and decoder for memory and its synthesis was done with Xilinx XST. Xilinx ISE Foundation 9.1i has been used for performing mapping, placing and routing. For behavioral simulation and place and route simulation ISE ...
Running Functional Simulation Simulation support for the RS Decoder IP core is provided for Aldec Active-HDL (Verilog and VHDL) simulator, Mentor Graphics ModelSim simulator. The functional simulation includes a configuration-specific behavioral model of the RS Decoder IP ...
Moreover, the decoder lends itself to the design methodologies which take advantage of the commercially available hardware behavioral modeling languages such as Verilog and VHDL and design synthesis tools. In accordance with another embodiment of the present invention, an All Neighbors LA-MLSE algorithm...