按照初始化时序,在200us时,mem_clk时钟稳定,开始初始化设置,设置完后,会产生一个初始化完成标志,local_init_done会拉高,没有拉高,可能有以下几个原因: 1.确认DDR2 IP核上的所有信号是否都用到了; 2.可能跟复位有关系; XXXXXX
首先你要确认DDR2 IP 核上的所有信号是否都用到了，我当时有过因为DM引脚没有分配造成初始化无法完成。然后就是确认硬件没有问题，例如DDR2芯片是好的，电压是正常的等，我当时因为DDR2 芯片有过问题，一直不能初始化完成，而且个人觉得现在DDR2芯片很多有问题。至于你里面问的三个问题，第一个问题，...
DDR3的IP核是FPGA编程中常用的一的IP,今天我们来聊聊DDR3的IP怎么仿真。使用环境:ISE调用IP:MIG7 Series /MIGVirtex-6and Spartan-6...glbl.v改为在ISE安装目录下的绝对路径,如下图; 2)打开modelsim工具,新建工程指到仿真文件下的sim文件夹;3)仿真时直接运行dosim.do,等待出波形图即可。
I'm using DDR2 hp memctrl IP within Stratix III, addressing 2 parallel HYB18T1G160C2F-3S (totaling to 32-bit data bus width), phy_clk = 200 MHz I'm currently facing the issue, that local_init_done signal is not going high reliably (sometimes it...
Devices always starting and working normal, but in a one moment local_init_done going LOW and after not going HIGH never. Only after global reset alt_mem_phy DDR2 controller release local_init_done ('1'). Device can working all day, but can work only few minutes. T...
I have built a DDR2 SDRAM v7.2 controlller, v7.2, using the Megawizard and a native interface. I have reviewed my schematic and pinout and it looks to be correct. The local_init_done is not going high. I verified this using Signal Tap. Could I have a bad 2GB SODIMM modul...
I'm using DDR2 hp memctrl IP within Stratix III, addressing 2 parallel HYB18T1G160C2F-3S (totaling to 32-bit data bus width), phy_clk = 200 MHz I'm currently facing the issue, that local_init_done signal is not going high reliably (sometimes it doe...
I'm using DDR2 hp memctrl IP within Stratix III, addressing 2 parallel HYB18T1G160C2F-3S (totaling to 32-bit data bus width), phy_clk = 200 MHz I'm currently facing the issue, that local_init_done signal is not going high reliab...