using this as a verilog module included in a design inside a vhdl wrapper, how do i get modelsim to pick up the dcfifo_mixed_widths ip block properly so it can run testbenches? // synopsys translate_off`timescale 1 ps / 1 ps// synopsys translate_onmodule parametrized_fi...
Hello, In the DCFIFO documentation i see that DCFIFO_MIXED_WIDTHS is supported for Arria 10 with several combination of widths of input and output
using this as a verilog module included in a design inside a vhdl wrapper, how do i get modelsim to pick up the dcfifo_mixed_widths ip block properly so it can run testbenches? // synopsys translate_off`timescale 1 ps / 1 ps// synopsys translate_onmodule p...