In the existing method, an extremely low power flip flop named topologically compressed flip flop is proposed. As compared with conventional type FFs, the FF reduces power dissipation by 75% at 0% data activity. The reduction is achieved by merging the logically equiv...
The average power consumption of proposed pulse triggered flip flop using pass transistor logic is 16uw and the number of transistors used 18.Index Terms: low power, pass ... P.Naveenasindhu,N.Manikandan 被引量: 0发表: 2015年 A low power dual-mode pulse triggered flip-flop using pass ...
Design of a Low Power Flip-Flop Using MTCMOS Technique This paper enumerates low power, high speed design of Flip-Flops having less number of transistors and only one transistor being clocked by short pulse tra... CD Sagar - 《International Journal of Computer Applications & Information Technolog...
if you want it to behave as a proper flip-flop you need a few more, so ten ain't unreasonable. If you're planning to make a ram bank you could go for dynamic memory and cut down on transistors a lot, but then you have to design a memory controller which is a whole headache of...
A Modified D Flip-flop with Deep Submicron Technology For future Electronic Systems,1Paneti. Mohan & 2P.C. Praveen Kumar, international Journal of Advanced Electrical and Electronics Engineering, (IJAEEE), vol.2, no.3, pp.2278-8948, 2013...
The transient and power analysis are obtained with operating voltage at 0.6V for the Double edge triggered D flip-flop and SISO shift register using system vision tool. There are many issues facing while integrating many number of transistors like short channel effect, power dissi...
According to the D- flip-flop of the present invention, the number of stacked transistors is reduced, it is maintained in the vicinity of the threshold voltage of pull-down transistors regardless of the bias voltage applied to the gate terminal of the pull-down transistor in the bias unit ...
A novel D-type flip-flop (DFF) with active inductive peaking powered by 0.7 V supply is proposed and implemented for low power communication. Forward bias (FB) technique is introduced for both the DFF and the active inductor in the clock buffer to effectively reduce the transistor threshold vo...
Key words:AlGaN/GaN;fluorine plasma treatment;inverter;NAND gate;D flip-flop DOI:10.1088/1674-4926/32/6/065001EEACC:2570 1.Introduction AlGaN/GaN high electron mobility transistors(HEMT) are excellent candidates for integrated circuits used in elevated temperature and radiation environments owing to ...
Design of 3-valued R-S & D type of flip-flops is described. A new clock is developed according to which circuit makes transition as well as retains present, past & former past information. The proposed flip-flops are constructed using clocked T-Gates that reduces the number of transis...