In the existing method, an extremely low power flip flop named topologically compressed flip flop is proposed. As compared with conventional type FFs, the FF reduces power dissipation by 75% at 0% data activity. The reduction is achieved by merging the logically equ...
Proposed in this paper is a low-power consumption D flip-flop circuit with asynchronous reset on the basis of Pseudo-CMOS logic gates, which consists of n-type a-IGZO TFTs (Thin Film Transistors), replaces the dio-deload in Pseudo-CMOS topology with dynamic load, and decreases the static...
D Flip Flop is primarily meant to provide delay as the output of this Flip Flop is same as the input It can easily made using a SR Flip Flop or JK Flip Flop
According to the D- flip-flop of the present invention, the number of stacked transistors is reduced, it is maintained in the vicinity of the threshold voltage of pull-down transistors regardless of the bias voltage applied to the gate terminal of the pull-down transistor in the bias unit ...
摘要: PROBLEM TO BE SOLVED: To provide a D flip-flop in which data are sent/received at a high speed between integrated circuits (DFFs), a clock skew caused in this case is reduced, and a latch error caused by the skew is prevented....
The present disclosure relates to a dynamic D flip-flop, a register, a chip, and a data processing apparatus. A dynamic D flip-flop is provided, including: an input terminal, config
A flip-flop includes a clock signal input, a data signal input, non-inverting and inverting outputs, a data acceptance unit, and a storage unit having a feedback loop with first and second inverter circuits having feedback to one another. The inverting output is coupled to the first inverter...
Novel Differential Flip-Flops Using Neuron-MOS Transistors Two new differential flip-flops using neuron-MOS transistors are presented, including one-latch single edge-triggered(IL-SET) flip-flop and one-latch doubl... G Hang,X Hu,D Zhang,... - IEEE Computer Society 被引量: 1发表: 2013年 ...
A D flip-flop with a reduced power product or reduced clock line capacitance is disclosed. The flip-flop includes a half-static slave stage or a master stage with clock gating by the input and output. The half-static slave stage an output inverter and a feedback element consisting of a ...
4. The circuit of claim 1 wherein the D flip-flop device is an ECL D flip-flop having a plurality of NPN transistors, implemented in bipolar or CMOS technology. 5. The circuit of claim 4 wherein each said latch comprises: a pair of input transistors, one said input transistor having ...