An emitter-function logic (EFL) D-type flip-flop modified with a non-linear load is presented, which allows for the programming of the bias current to match transition time (15–200 ns) to the functional requirements at minimum power consumption (20 mW-200μW) while maintaining the ...
IMPLEMENTATION OF LOW POWER D-FLIPFLOP USING 45NM CMOS TECHNOLOGY Designing low power devices is now a major sector of research due to increased demand for portable devices. Because MOS devices are widespread, there is a great need for less energy-consuming circuits, especially for portable devices...
The particular interval during which a flip-flop is susceptible is dependent on the logic state of the data input line, the implementation technology of the flip-flop, and the amplitude of the disturbing signal. The total width of the susceptibility intervals is a device parameter that can be ...
微处理机 MICROPROCESSORS 一种抗单粒子翻转的D触发器 杨玉飞 (中国电子科技集团公司第四十七研究所,沈阳110032) 摘要:以互锁存储单元(DICE)结构为基础,采用0.35μmCMOS工艺,设计了一种具有抗单 粒子翻转的带置位端的D触发器。通过将数据存放在不同节点以及电路的恢复机制,使单个存 储节点具有抗单粒子翻转的能力。
7) T.Uemura & T.Baba "A 3-Valued D-Flip-Flop & Shift Register using Multiple Junction Surface Tunneling Transistors" IEEE Trans. On electron devices,Vol 49, No.8, P.P.1336-1340 August 2002. 8) Prosser,F;Wu,X; Chen ,X; "CMOS Ternary Flip-Flops & Their ...
D-type flip-flop (hardware) A digital logic device that stores the status of its "D" input whenever its clock input makes a certain transition (low to high or high to low). The output, "Q", shows the currently stored value.
Implementation of subthreshold D flip-flops in layout is one step closer to having a subthreshold building block library. The task for this thesis is to implement D flip-flop blocks, which are highly suitable for subthreshold operation in layout. These are the PowerPC 603, C$^2$MOS, a ...
The output of a JK-flip flop (JK) and a D-flip-flop (D1) are fed to a NOR gate (N1) which in turn feeds a second D- flip-flop (D2) whose output goes, via a second NOR-gate (N2) to an OR-gate (O1) and to the output terminal (A). An additional three OR-gates and ...
Product Folder Sample & Buy Technical Documents Tools & Software Support & Community CD4013B SCHS023E – NOVEMBER 1998 – REVISED SEPTEMBER 2016 CD4013B CMOS Dual D-Type Flip-Flop 1 Features •1 Asynchronous Set-Reset Capability • Static Flip-Flop Operation • Medium-Speed Operation: 16 ...
for clock rates ranging from 100to 300MHz.In the SMIC 0 13 m CMOS technology,a function generator is implemented using SAERD.Simulation result shows a total power saving of up to 17 1%as compared to the implementation using the conventional D flip -flops MSD (master salve D flip -flop)....