Within a method for forming a memory cell structure there is provided a field effect transistor (FET) device having electrically connected to one of its source/drain regions a storage capacitor and electrically connected to the other of its source/drain regions a bitline stud layer separated from...
The air gap void provides for attenuated bitline to capacitor structure capacitive coupling, and thus enhanced performance of the memory cell structure.doi:US6501120 B1Yeur-Luen TuChia-Shiung TsaiMin-Hwa ChiUSUS6501120 Jan 15, 2002 Dec 31, 2002 Taiwan Semiconductor Manufacturing Company, Ltd ...
CONSTITUTION: While manufacturing a semiconductor device having a capacitor with lower bit line structure, the bit line is formed after forming the capacitor so that the bit line is connected to the cell area and to the core/peripheral area of n+/p+, thus realizing the simplified process. ...
Within a method for fabricating a dynamic random access memory (DRAM) cell structure there is first anisotropically sequentially etched a blanket hard mask layer and a blanket capacitor plate layer which both cover a bit-line source/drain region within the dynamic random access memory (DRAM) cell...
Within a method for fabricating a dynamic random access memory (DRAM) cell structure there is first anisotropically sequentially etched a blanket hard mask layer and a blanket capacitor plate layer which both cover a bit-line source/drain region within the dynamic random access memory (DRAM) cell...
An opening is etched through a third and the second insulating layers between the capacitors to the bit line contact plug and filled with a conducting layer to form a bit line to complete fabrication of a DRAM with CUB cell in an integrated circuit device....
US6500706 2001年3月19日 2002年12月31日 Taiwan Semiconductor Manufacturing Company Bit-line interconnection scheme for eliminating coupling noise in stack DRAM cell with capacitor under bit-line (CUB) in stand-alone or embedded DRAMUS6500706 * Mar 19, 2001 Dec 31, 2002 Taiwan Semiconductor ...