When I compile my design which use two plls in a EP4CE55F device, I have a cirtical warning as following: Critical Warning (176598): PLL
I am struck up with one of the critical warning issue in the PLL. Critical Warning (176598): PLL "pll:pllInst|altpll:altpll_component|pll_altpll:auto_generated|pll1" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_AJ16" Can anyone plea...