Critical Warning (176598): PLL "pll:pllInst|altpll:altpll_component|pll_altpll:auto_generated|pll1" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_AJ16" Can anyone please help me to fix this critical warning issue. Regards, Kishore Kumar...
I am struck up with one of the critical warning issue in the PLL. Critical Warning (176598): PLL "pll:pllInst|altpll:altpll_component|pll_altpll:auto_generated|pll1" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_AJ16" Can anyone plea...
in my design am using dadicated clock pin as a sourse to pll in cyclone iv fpga still m finding critical warning. i tried back-annotation for all the banks still m getting same critical warning. in that case whatneeds to be done??? Critical Warning (176598): PLL "...