Section 11.2 addresses two topics: detection of errors in logic design and formal verification, the latter being a method to verify logic design by mathematical reasoning. Section 11.3 introduces the use of Built-in Self-Test (BIST) method to monitor circuit delays in a VLSI precisely enough to...
Generate test cases t(INPUT) for each path in Pu. Finally, manually verify the expected values for all t(INPUT) and complete them as t(INPUT,EXPECT). Pu=Pt−Pc 2. Software description PC-TRT is an effective test case reuse tool comprising four modules: static analysis, dynamic analysis...
This invention offers a unique contribution to what is termed Functional Verification in VLSI (Very Large Scale Integration). Functional Verification denotes a procedure for determining that a design conforms to its specification. Digital simulation is the most common functional verification technique for...
verify RTL source code and design properties are known as “model checkers.” Design properties to be verified include specifications and/or requirements that must be satisfied by the circuit design. Since mathematical properties define the design requirements in pure mathematical terms, this enables ...
RISC-V processors based on increasingly popular open standard instruction set architecture (ISA) are challenging to verify because of their optional features, implementation flexibility, and custom extensions. However, their uniformity and modular design present a unique opportunity to develop a high-...
In our work, we consider the write and read register function as a kernel of a microprocessor; similar to a sequential machine, and we use the checking experiment to verify the kernal based on the fault models. Then we use the kernal for testing other instructions. Our approach consists of...
Zambotti et al., “LSI-CP: VLSI microprocessor emulates military processors”, ACM, 1984. Lachish, Oded et al., “Hole Analysis for Functional Coverage Data,” 39th Design Automation Conference, DAC 2002, Jun. 10-14, 2002, New Orleans, Louisiana. Piziali, Andrew, “Functional Verificatio...
P. Hayes, “Hierarchical Modeling for VLSI Circuit Testing,” Boston: Kluwer, 1990, p. 159, which is hereby incorporated by reference. Implication analysis works as follows. Initially, the hierarchical design database 712 and the DI optimimization module 714 are consulted to determine whether a...
the RTL modules when changes are made to the RTL modules in the IC design; generating a plurality of regression tests dynamically for these affected RTL modules based on their corresponding coverage data; running the dynamically generated regression tests to verify the changes made in the IC ...
They also create a simple testbench to verify the basic functionalities of the circuit. Verification engineers (whose number is usually larger compared to the number of designers) are in charge of creating the verification environment and a testbench (referred to in Figure 7 as “simulation ...