Enter Property SystemVerilog already has amechanismfor defining and detecting any sequence of events. SystemVerilog also provides a way to use the sequences to create aproperty. We have already used such proper
sequence块和property块都有name,使用assert调用时都是:“assert property(name);” 在SVA中,sequence块一般用来定义组合逻辑断言,而property一般用来定义一个有时间观念的断言,它会常常调用sequence,一些时序操作如“|->”只能用于property就是这个原因。 注:以下介绍的SVA语法,既可以写在sequence中,也可以写在property...
In module context: assert property (<expression>); and within an always block: assert(<expression>);. It is transformed to an $assert cell. The assume, restrict, and cover statements from SystemVerilog are also supported. The same limitations as with the assert statement apply. The keywords ...