503 11 0 fMAX (MHz)(2) Efinity® Version(3) clk axi_clk clk_byte_hs clk_pixel 415 453 359 377 2021.2 Functional Description The MIPI CSI-2 RX Controller consists of a RX D-PHY block, lane aligner, control status registers, ECC and CRC checkers, depacketizer, and byte-to pixel ...
mipi_csi_0: csi@58227000 { compatible = "fsl,mxc-mipi-csi2"; reg = <0x0 0x58227000 0x0 0x1000>, /* CSI0 Controler base addr */ <0x0 0x58221000 0x0 0x1000>; /* CSI0 Subsystem CSR base addr */ interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; interrupt-parent = <&irqsteer_csi>; cl...
FLASH_CLK - 26.67MHz Please see below my clock config struct: clock_manager_user_config_t clockMan1_InitConfig0 = { /*! @brief Configuration of SIRC */ .scgConfig = { .sircConfig = { .initialize = true, /*!< Initialize */ /* SIRCCSR */ .enableInStop = false, /*!< SIRCSTE...
FLASH_CLK - 26.67MHz Please see below my clock config struct: clock_manager_user_config_t clockMan1_InitConfig0 = { /*! @brief Configuration of SIRC */ .scgConfig = { .sircConfig = { .initialize = true, /*!< Initialize */ /* SIRCCSR */ .enableInStop = false, /*!< SIRCSTEN...
e203_clk_ctrl Clock control module e203_reset_ctrl Reset control module e203_irq_sync Asynchronous interrupt signal sync module e203_itcm_ctrl ITCM control module e203_dtcm_ctrl DTCM control module e203_core Main logic top module of core e203_ifu Top module of fetch unit e203_exu Top module ...
SysTick timer - Driven by SYSTICCLK (LOCO) or ICLK. Table 1.2 Memory Feature Code flash memory Data flash memory Option-setting memory SRAM Functional description Maximum 256-KB code flash memory. See section 44, Flash Memory in Userʼs Manual. 8-KB data flash memory. See section ...
CLKIN PERIPHCLK PERIPHCLKEN N=3 Figure 2-5 Clocking example on Cortex-A5 MPCore peripherals AXI interface clocking The SCU AMBA AXI interface supports integer ratios of the CLKIN frequency (1:1, 2:1, 3:1, ...). These ratios are configured through external clock enable signals. In all ...
clk_i Clock input rst_i Async reset, active-high. Reset memory / AXI interface. rst_cpu_i Async reset, active-high. Reset CPU core (excluding AXI / memory). axi_t_* AXI4 slave interface for access to 64KB TCM memory. axi_i_* AXI4-Lite master interface for CPU access to peripheral...
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