All of the software (Makefile, C++) code in this repository is released under theGPLv3. The Verilog RTL code generated by this core generator is licensed underLGPLv3. If these conditions are not sufficient for your needs, other licenses terms may be purchased.
As you might expect, [Armeen] used a lot of Opal Kelly hardware and software in the project. But the Verilog code (available onGitHub) shows a lot of interesting things including some very practical example code for using Xilinx CORDIC IP, which is a great way to do high-order math usin...