Traditionally many boards used local definitions for SRAM base address and size (like SRAM_BASE, SRAM_LEN and/or SRAM_SIZE), while the (now) "official" names are CONFIG_SYS_SRAM_BASE and CONFIG_SYS_SRAM_SIZE. The corresponding code in arch/powerpc/lib/board.c was board specific, and ha...
* The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three Expand Down Expand Up @@ -611,7 +611,7 @@ void enable_caches(void) icache_enable(); dcache_enable(); } #endif /* CONFIG_SYS_DCACHE_OFF */ #endif /* !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */ #ifdef CONFI...
# CONFIG_ESP_SYSTEM_ESP32_SRAM1_REGION_AS_IRAM is not set # end of Non-backward compatible options # end of Memory # # Trace memory # # CONFIG_ESP32_TRAX is not set CONFIG_ESP32_TRACEMEM_RESERVE_DRAM=0x0 # end of Trace memory # CONFIG_ESP_SYSTEM_PANIC_PRINT_HALT is...
# CONFIG_SRAM is not set # CONFIG_PCI_ENDPOINT_TEST is not set # CONFIG_C2PORT is not set # # EEPROM support # # CONFIG_EEPROM_AT24 is not set # CONFIG_EEPROM_LEGACY is not set # CONFIG_EEPROM_MAX6875 is not set # CONFIG_EEPROM_93CX6 is not set # CONFIG_EEPROM...
The table’s layout is quite simple.Each line creates a mapping of virtual addresses to physical addresses.The syntax is: Base virtual address, base physical address, size.Let’s take an example from the Mainstone BSP: DCD0x80000000, 0xA0000000,64; MAINSTONEII: SDRAM (64MB). ...
0000:00:14.2 RAM memory: Intel Corporation Alder Lake PCH Shared SRAM (rev 01) 0000:00:14.3 Network controller: Intel Corporation Device 51f1 (rev 01) 0000:00:15.0 Serial bus controller: Intel Corporation Alder Lake PCH Serial IO I2C Controller #0 (rev 01) 0000:00:16.0 Communication ...
# Default configuration values for OP-TEE core (all platforms).## Platform-specific overrides are in core/arch/arm32/plat-*/conf.mk.# Some subsystem-specific defaults are not here but rather in */sub.mk.## Configuration values may be assigned from multiple sources.# From higher to lower ...
当u-boot被download到nor flash或被copy到内部sram时,假设被copy到的地址是0x907000,那么此时_start的地址是0x907000,此时就需要将自身copy到TEXT_BASE地方。 当u-boot本身就被download sdram的TEXT_BASE定义的地址出,那么此时_start本身的地址就是0x27800000了,所以和TEXT_BASE比较的结果相等而不用作自...
void IAP_Set(void) { uint32_t i = 0; /* Relocate by software the vector table to the internal SRAM at 0x20000000 ***/ /* Copy the vector table from the Flash (mapped at the base of the application load address 0x08002800) to the base address of the SRAM at 0x20000000. */ for...
The table’s layout is quite simple. Each line creates a mapping of virtual addresses to physical addresses. The syntax is: Base virtual address, base physical address, size. Let’s take an examplefromthe Mainstone BSP: DCD 0x80000000, 0xA0000000, 64 ; MAINSTONEII: SDRAM (64MB). ...