Are you writing Verilog? What is "bit"? 0 Kudos Copy link Reply Altera_Forum Honored Contributor II 11-15-2012 04:42 PM 2,447 Views I am writing SystemVerilog. The code worked fine in Modelsim, but got error in Quartus. :) 0 Kudos Copy link Reply Alte...
I am writing SystemVerilog. The code worked fine in Modelsim, but got error in Quartus. :) Translate 0 Kudos Copy link Reply Altera_Forum Honored Contributor II 11-15-2012 09:01 PM 2,504 Views Array = {6'd4, 6'd5} works for me. Translate 0 Kudos Copy link ...