riscv_script source tools_libyuv unit_test util Makefile color.cc compare.cc cpuid.c i444tonv12_eg.cc psnr.cc psnr.h psnr_main.cc ssim.cc ssim.h yuvconstants.c yuvconvert.cc .clang-format .gitignore .gn .vpython .vpython3 AUTHORS Android.bp Android.mk BUILD.gn CM_linux_packages....
Change https://go.dev/cl/514596 mentions this issue: cmd/compile: implement float min/max in hardware for amd64 and arm64 Contributor gopherbot commented Aug 1, 2023 Change https://go.dev/cl/514775 mentions this issue: cmd/compile: implement float min/max in hardware for riscv64 gopher...
Cortex-A76 64-bit quad-core (ARM v8) @2.4GHz RP2350 dual-core Arm Cortex-M33 / Hazard3 RISC-V cores RP2350 dual-core Arm Cortex-M33 / Hazard3 RISC-V cores Cortex-A72 (ARM v8) 64-bit @1.5GHz Cortex-A76 64-bit @2.4GHz RP2040 dual-core Arm Cortex-M0+ Cortex-A53 64-bit RP20...
And while we have been experimenting a bit with running Spin on RISC, we haven't really had the bandwidth or requirement to build a production build for those yet. Are you interested in a specific operating system or CPU architecture? Would love to understand your scenario. Dave Cutler: The...
32 bit Single-Core @ 240Mhz ARM Cortex-M3 @ 24 / 36 / 48 / 72 MHz ARM Cortex-M4F @ 170 MHz FPU, DSP instructions 32-bit ARM Cortex M3 72MHz max Tensilica LX106 32 bit @ 80 MHz (up to 160 MHz) NXP IMXRT1062DVJ6A ARM Cortex-M7 at 600 MHz with FPU (32 bit float and 64...
AC_MSG_ERROR([Could not link conftestf.o and conftest.o]) fi else AC_MSG_ERROR([Could not compile conftestf.f]) fi else AC_MSG_ERROR([Could not compile conftest.c]) fi done ${RM} -f conftest* if test "$ac_cv_ctype_fortran" = no ; then ...
0.20.2 '@esbuild/linux-riscv64': 0.20.2 '@esbuild/linux-s390x': 0.20.2 '@esbuild/linux-x64': 0.20.2 '@esbuild/netbsd-x64': 0.20.2 '@esbuild/openbsd-x64': 0.20.2 '@esbuild/sunos-x64': 0.20.2 '@esbuild/win32-arm64': 0.20.2 '@esbuild/win32-ia32': 0.20.2 '@esbu...