1, where we refer to the Verilog-A model as “Vos Tester”. The Vos Tester block provides all Limitations of conventional techniques In order to illustrate the limitations of conventional offset simulation tech
32-bit register value Z112by the comparator110to determine if the result108equals the value of register Z112. The output114of the comparator110indicates whether the two values are equal to each other. An example simulation of the circuit ofFIG. 1, using a Verilog model, is shown inFIG. ...
1. A successive approximation analog-to-digital converter (ADC), comprising: an adjustable voltage source that applies an adjustable voltage to an input of a comparator of the ADC to cancel an offset of the ADC; and a control that suspends adjustments of the adjustable voltage when the adjustab...